Hendrik Krause

Introduction

Starting in 2029, the LHC will become the High-Luminosity LHC (HL-LHC) and will operate with an instantaneous luminosity seven times higher than the design parameter of the collider, leading to an inconceivable average of 200 simultaneous collisions per bunch crossing (every 25 ns). Among the hundreds of millions of collisions produced by the HL-LHC each second, only a handful of them contain potentially interesting physics and therefore need to be scrutinized. The large amount of data produced by the detector per second represents multiple terabytes (Tb) of information, which cannot be recorded on tape nor inspected with computers. Therefore, this selection at the input rate of 40 MHz may only be performed by a dedicated, custom-designed electronics system called the Level-1 Trigger (L1T), reducing this rate down to 750 kHz. For the first time, both tracking and highly granular information from the calorimeters and from the muon systems can be exploited at the L1T. The L1T key feature is the implementation of a Correlator Trigger designed to run a particle-flow algorithm used to reconstruct and identify precisely the particle event content. Additionally, trigger algorithms enter a new era of sophistication with the use of machine learning approaches or unsupervised learning techniques now possible to be implemented on FPGAs. The L1T system architecture has been designed to process efficiently the hundreds of Tb/s input bandwidth, relying on state-of-the-art FPGAs and high-speed optical links reaching up to 25 Gb/s. The data processing is carried out by thousands of generic processing cards based on the Advanced Telecommunications Computing Architecture (ATCA) technology. Intensive demonstration tests in various centers around the world have begun, and a larger-scale integration of the system at CERN is on its way. Once installed in the service cavern during Long Shutdown 3 in 2027, this system will offer extraordinary ways to select interesting physics phenomena from all collisions.

Research Plan

One of such generic-processing cards is called Serenity; it was developed by the Karlsruhe Institute of Technology in cooperation with Imperial College London. It is designed to be compatible with the connectivity requirements of different CMS sub-detector systems. Designing and bringing into operation such complex boards requires large and dedicated efforts on the firmware and software infrastructure components that allow operating the boards in all those potential scenarios. KIT is particularly involved in two major projects at CMS, the Silicon Tracker and the High-Granularity Calorimeter, both of which have plans to use the Serenity board in their readout architecture of the detector modules and the data reconstruction flow in the L1T. Particularly, I will program the high-speed FPGAs and the System-on-Chip (SoC) devices present in the Serenity board to bring the existing firmware implementations into a realistic form targeting a large-scale test with multi-detector modules. Similarly, the firmware implementations should target the final full interconnectivity requirements with other back-end boards in the L1T to perform system-level multi-board integration tests.