Shalina Figuli

Information

Institute: ITIV
Room: 126 (Building 30.10)
Phone: +49 721 608-45282
Email: shalina.ford@kit.edu
Website: http://www.itiv.kit.edu/english/21_3355.php

Curriculum Vitae

• Born in October 1989
• Study of Electrical Engineering (VLSI Design) at Karunya University, Coimbatore (India)
• Obtaining bachelor of technology (B.Tech.) degree in May 2011
• Topic of bachelor thesis: Retrofitting of Relay Logic Based Stud Welding Machine using Programmable Logic Controller
• Obtaining master of technology (M.Tech.) degree in May 2013
• Topic of master thesis: Bringing Accuracy to Open Virtual Platforms (OVP): A Safari from High-Level Tools to Low-Level Microarchitectures
• As Member of Scientific Staff at ITIV since September 2013
• As Doctoral Fellow of KSETA since July 2015

Research

• Architectures and tools for highly efficient system-on-chip
• Design and Evaluation of an FPGA based Ultra High Speed Data Communication System for Particle Detectors

Publications

• G. Shalina, P. Figuli, J. Becker
  Parametric Design Space Exploration for Optimizing QAM Based High-speed Communication
  In IEEE/CIC International Conference on Communications in China, 2015
Abstract: The growing demands on high-speed data transmission over long distances require optimized communication solutions with bandwidth efficient modulation techniques like Quadrature Amplitude Modulation (QAM). However, the various design parameters of QAM based communication systems are conflicting each other and the complex interdependence makes it difficult and time consuming to appropriately tune the parameters towards an optimal solution for a given set of constraints. Therefore, throughout this paper we analyze the various conflicting design parameters of QAM and derive objective optimized trade-offs. More specifically we study in detail the effects and interdependencies of parameters in the matched filter, the Forward Error Correction (FEC) code pair and the modulation order and span the design and solution space through experimental and numerical results. We discuss the observed effects and show how a selection of parameters can be concluded under various constraints. Furthermore, a pareto analysis on our design space points out the best combinations of modulation order, filter and FEC for maximizing the performance under various Signal-to-Noise Ratio (SNR) conditions of the channel. For instance, if the channel is constrained by an SNR of 10dB and the tolerable Bit Error Rate (BER) is 10^(-3), then 16-QAM with a required 2/3 FEC yields even a 33.3% higher performance than 64-QAM with a required 1/3 FEC. Thus, the outcomes of this paper are a comprehensive elaboration on the cross-effects of conflicting design parameters and a set of optimized solutions under various constraints.
• E. Sotiriou-Xanthopoulos, G. Shalina, P. Figuli, K. Siozos, G. Economakos, J. Becker
  A Power Estimation Technique for Cycle-Accurate Higher-Abstraction SystemC-based CPU Models
  In International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2015
Abstract: Due to the ever-increasing complexity of embedded system design and the need for rapid system evaluations in early design stages, the use of simulation models known as Virtual Platforms (VPs) has been of utmost importance as they enable system modeling at higher abstraction levels. Since a typical VP features multiple interdependent components, VP libraries have been utilized in order to provide off-the-shelf models of commonly-used hardware components, such as CPUs. However, CPU power estimation is not adequately supported by existing VP libraries. In addition, existing power characterization techniques require architectural details which are not always available in early design stages. To address this issue, this paper proposes a technique for power annotation of CPU models targeting SystemC/TLM libraries in order to enable the accurate power estimation at higher abstraction levels. By using a set of benchmarks on a power-annotated SystemC/TLM model of Xilinx Microblaze soft-processor, it is shown that the proposed approach can achieve accurate power estimation in comparison to the real-system power measurements as the estimation error ranges from 0.47% up to 6.11% with an average of 2%.
• K. Siozos, P. Figuli, H. Sidiropoulos, C. Tradowsky, K. Maragos, G. Shalina, D. Soudris, J. Becker
  TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools (Nominated as Best Paper Candidate)
  In Applied Reconfigurable Computing, Band 9040, S. 103-114, 2015
Abstract: This paper presents an on-going collaboration project, named TEAChER for providing breakthrough knowledge to students and young researchers on reconfigurable computing and advanced digital systems. The project is intended to cover topics like architectures and capabilities of field-programmable gate arrays, languages for the specification, modeling, and synthesis of digital systems. Furthermore design methods, computer-aided design tools, reconfiguration techniques and practical applications are taught. The virtual laboratory enables the remote students to easily interact with a set of reconfigurable platforms in order to control experiments through the internet. By using the user-friendly interface, the remote user can change predefined system parameters and observe system response either in textual, or graphical format. In addition such a virtual laboratory includes a booking system, which enables remote users to conduct experiments in advance.
• G. Shalina, T. Bruckschloegl, P. Figuli, C. Tradowsky, G. Almeida, J. Becker
  Bringing Accuracy to Open Virtual Platforms (OVP): A Safari from High-Level Tools to Low-Level Microarchitectures
  In IJCA Proceedings on International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences, Band ICIIIOES, S. 22-27, 2013
Abstract: The aggressive technology scaling in the feature size has propelled the designers to integrate millions of transistors in a single die. Thus Multi-Processor System on Chip (MPSoC) has become the irrefutable elucidation to meet the demands of parallel computing in the domain of embedded systems. The gap between software development and actual hardware model has led to the emergence of virtual platforms so that the performance status can be improved even before the Register Transfer Logic (RTL) of the hardware is actualized. This paper presents a framework to bring accuracy to Open Virtual Platforms (OVP). Several architectures are modeled using this functional simulator and they are profiled to achieve a good accuracy/speed tradeoff. The accuracy of the simulation results is further enhanced by tuning profiling parameters and introducing an empirical correction factor which compensates the imprecisions of OVP that arise e. g. from missing simulated bus- and memory access times.

KSETA Reports

• 2015