- S. Baehr, O. Sander, M. Heck, M. Feindt, J. Becker
A framework for porting the NeuroBayes machine learning algorithm to FPGAs
In Topical Workshop on Electronics for Particle Physics (TWEPP) 2015, 2015
- S. Baehr, O. Sander, M. Heck, C. Pulvermacher, M. Feindt, J. Becker
Online-Analysis of Hits in the Belle-II Pixeldetector for Separation of Slow Pions from Background
In CHEP 2015 Computing in High Energy Physics Conference, 2015
- D. Adam, S. Tverdyshev, C. Rolfes, T. Sandmann, S. Baehr, O. Sander, J. Becker, U. Baumgarten
Two Architecture Approaches for MILS Systems in Mobility Domains (Automobile, Railway and Avionik)
In International Workshop on MILS: Architecture and Assurance for Secure Systems (MILS 2015), 2015
Zusammenfassung:
Systems with mixed and independent levels of security and safety become more and more important in the future. In the German funded Bundesministerium fuer Bildung und Forschung (BMBF) research project ARAMiS (Automotive, Railway and Avionic Multicore Systems) different industry and scientiffic partners concerned on using multi-core processor for different security and safety critical use-cases. This paper describes the motivation and use-cases behind the research actives in different mobility domains. Also two detailed descriptions and a comparison of two implementation for Multiple Independent Levels of Security and Safety (MILS) systems in mobility domains are included. In the end of the paper a outlook is given on potential further research activities on this research topic.
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Zusammenfassung:
Systems with mixed and independent levels of security and safety become more and more important in the future. In the German funded Bundesministerium fuer Bildung und Forschung (BMBF) research project ARAMiS (Automotive, Railway and Avionic Multicore Systems) different industry and scientiffic partners concerned on using multi-core processor for different security and safety critical use-cases. This paper describes the motivation and use-cases behind the research actives in different mobility domains. Also two detailed descriptions and a comparison of two implementation for Multiple Independent Levels of Security and Safety (MILS) systems in mobility domains are included. In the end of the paper a outlook is given on potential further research activities on this research topic.
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- D. Reinhardt, D. Adam, E. Lubbers, R. Amarnath, R. Schneider, S. Gansel, S. Schnitzer, C. Herber, T. Sandmann, H. U. Michel, D. Kaule, D. Olkun, M. Rehm, J. Harnisch, A. Richter, S. Baehr, O. Sander, J. Becker, U. Baumgarten, H. Theiling
Embedded Virtualization Approaches for Ensuring Safety and Security within E/E Automotive Systems
In Embedded World Conference, 2015
Zusammenfassung:
Automotive E/E systems are subject to several conflicting non-functional requirements. Monetary costs, shorter technology and time-to-market cycles and rising restrictions to energy consumption build a subset of them. Furthermore, existing safety and security criteria must be met. Because of future game
changers, like highly automated driving or share-economy scenarios, the relevance to incorporate such non-functional requirements within the product development will increase.
Within the ARAMiS (Automotive, Railway and Avionic Multicore Systems) project funded by BMBF, different use-cases of the industry and scientific partners were analyzed. The project goal is to enable multicore systems across mobility domains and show different technical concept implementations and detail the achieved improvements over traditional systems.
In ARAMiS, a special focus is placed on embedded virtualization technologies for ensuring safety and security according to existing standards (ISO26262). For isolation purposes and flexible software relocation of Enterprise Systems, hypervisors are already an attractive and proven approach. Here, we analyze virtualization methods within real-time systems for hardware and software to enable embedded hypervisors for automotive needs.
Within this paper, we present results arising from the work in the automotive domain within the ARAMiS research project. For that purpose, we have developed OEM specific demonstrator platforms for evaluation purposes to reflect typical automotive use-cases. These platforms are implemented on different hardware controllers, performance classes and mission scenarios. Specifically, we analyze the operation of mixed integrity systems.
As a result, the commonalities and technical challenges between demonstrator platforms are identified, and the suitability of virtualization technologies for embedded multicore controllers for automotive E/E systems is discussed. The results enable next generation scenarios for industry partners and provide guidance for future research activities.
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Zusammenfassung:
Automotive E/E systems are subject to several conflicting non-functional requirements. Monetary costs, shorter technology and time-to-market cycles and rising restrictions to energy consumption build a subset of them. Furthermore, existing safety and security criteria must be met. Because of future game
changers, like highly automated driving or share-economy scenarios, the relevance to incorporate such non-functional requirements within the product development will increase.
Within the ARAMiS (Automotive, Railway and Avionic Multicore Systems) project funded by BMBF, different use-cases of the industry and scientific partners were analyzed. The project goal is to enable multicore systems across mobility domains and show different technical concept implementations and detail the achieved improvements over traditional systems.
In ARAMiS, a special focus is placed on embedded virtualization technologies for ensuring safety and security according to existing standards (ISO26262). For isolation purposes and flexible software relocation of Enterprise Systems, hypervisors are already an attractive and proven approach. Here, we analyze virtualization methods within real-time systems for hardware and software to enable embedded hypervisors for automotive needs.
Within this paper, we present results arising from the work in the automotive domain within the ARAMiS research project. For that purpose, we have developed OEM specific demonstrator platforms for evaluation purposes to reflect typical automotive use-cases. These platforms are implemented on different hardware controllers, performance classes and mission scenarios. Specifically, we analyze the operation of mixed integrity systems.
As a result, the commonalities and technical challenges between demonstrator platforms are identified, and the suitability of virtualization technologies for embedded multicore controllers for automotive E/E systems is discussed. The results enable next generation scenarios for industry partners and provide guidance for future research activities.
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- D. V. Vu, O. Sander, T. Sandmann, J. Heidelberger, S. Baehr, J. Becker
On-Demand Reconfiguration for Coprocessors in Mixed Criticality Multicore Systems
In 7th International Workshop on Dependable Many-Core Computing (DMCC 2015), 2015
Zusammenfassung:
Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions. In a previous work, we proposed a concept that leverages the advantages of FPGA's partial reconfiguration in heterogeneous mixed criticality multicore systems. The basic idea how to handle the partial reconfiguration transparently for non-critical tasks, while providing full control and a predictable behavior for safety relevant tasks was described. In this paper, we focus on the on-demand partial reconfiguration of non-critical coprocessor and its implementation details. Our prototype is implemented on an Intel multicore system and a Xilinx Virtex-7 FPGA connected via PCI Express (PCIe), taking advantage of the Single-Root I/O Virtualization (SR-IOV) capabilities in modern PCIe implementations. Experimental results show that our concept achieves significantly shorter reconfiguration time with lower variance under various load situations.
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Zusammenfassung:
Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions. In a previous work, we proposed a concept that leverages the advantages of FPGA's partial reconfiguration in heterogeneous mixed criticality multicore systems. The basic idea how to handle the partial reconfiguration transparently for non-critical tasks, while providing full control and a predictable behavior for safety relevant tasks was described. In this paper, we focus on the on-demand partial reconfiguration of non-critical coprocessor and its implementation details. Our prototype is implemented on an Intel multicore system and a Xilinx Virtex-7 FPGA connected via PCI Express (PCIe), taking advantage of the Single-Root I/O Virtualization (SR-IOV) capabilities in modern PCIe implementations. Experimental results show that our concept achieves significantly shorter reconfiguration time with lower variance under various load situations.
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- F. Bapp, O. Sander, T. Sandmann, D. V. Vu, S. Baehr, J. Becker
Adapting Commercial Off-The-Shelf Multicore Processors for Safety-Related Automotive Systems Using Online Monitoring
In SAE 2015 World Congress and Exhibition, 2015
Zusammenfassung:
Multicores, being the latest state-of-the-art technology, gain more and more importance in automotive and aerospace systems. This technology will not only be used in infotainment and non-safety-critical applications but will also be introduced in upcoming safety-critical systems. At the moment, various commercial off-the-shelf processors are available that are, however, not built for such applications. In order to ensure correct system behavior, online monitoring can be used for processors targeting infotainment or general purpose applications. The cores and other bus masters within the MPSoC compete for the exclusive use of shared resources like a memory controller. It is of high importance to provide guarantees of usage in such cases, e.g. in terms of access time and rates. For this purpose we present an online monitoring based on a commercial off-the-shelf multicore processor that provides knowledge about the usage of the direct memory access (DMA) controller in terms of accesses and activation sources. Furthermore, with this information, conclusions about the memory controller workload are drawn. The concept is implemented by using Freescale’s i.MX6 Quad platform, which is targeting automotive infotainment. This paper aims to show how such general purpose multicore processors can be partly adapted to provide evidence for safety related systems.
BibTeX: Anzeigen
Zusammenfassung:
Multicores, being the latest state-of-the-art technology, gain more and more importance in automotive and aerospace systems. This technology will not only be used in infotainment and non-safety-critical applications but will also be introduced in upcoming safety-critical systems. At the moment, various commercial off-the-shelf processors are available that are, however, not built for such applications. In order to ensure correct system behavior, online monitoring can be used for processors targeting infotainment or general purpose applications. The cores and other bus masters within the MPSoC compete for the exclusive use of shared resources like a memory controller. It is of high importance to provide guarantees of usage in such cases, e.g. in terms of access time and rates. For this purpose we present an online monitoring based on a commercial off-the-shelf multicore processor that provides knowledge about the usage of the direct memory access (DMA) controller in terms of accesses and activation sources. Furthermore, with this information, conclusions about the memory controller workload are drawn. The concept is implemented by using Freescale’s i.MX6 Quad platform, which is targeting automotive infotainment. This paper aims to show how such general purpose multicore processors can be partly adapted to provide evidence for safety related systems.
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- O. Sander, T. Sandmann, S. Baehr, D. V. Vu, E. Lubbers, J. Becker
A Flexible Interface Architecture for Reconfigurable Coprocessors in Embedded Multicore Systems using PCIe Single-Root I/O Virtualization
In The 2014 International Conference on Field-Programmable Technology (ICFPT 2014), 2014
Zusammenfassung:
Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions. In this paper, we propose a flexible interface architecture with low overhead for coupling reconfigurable coprocessors to highperformance general-purpose processors, allowing customized yet efficient construction of heterogeneous processing systems. Our implementation is based on PCI Express (PCIe) and optimized for virtualized systems, taking advantage of the SR-IOV capabilities in modern PCIe implementations. We describe the interface architecture and its fundamental technologies, detail the services provided to individual coprocessors and accelerator modules, and quantify key corner performance indicators relevant for virtualized applications.
BibTeX: Anzeigen
Zusammenfassung:
Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions. In this paper, we propose a flexible interface architecture with low overhead for coupling reconfigurable coprocessors to highperformance general-purpose processors, allowing customized yet efficient construction of heterogeneous processing systems. Our implementation is based on PCI Express (PCIe) and optimized for virtualized systems, taking advantage of the SR-IOV capabilities in modern PCIe implementations. We describe the interface architecture and its fundamental technologies, detail the services provided to individual coprocessors and accelerator modules, and quantify key corner performance indicators relevant for virtualized applications.
BibTeX: Anzeigen
- D. V. Vu, O. Sander, T. Sandmann, S. Baehr, J. Heidelberger, J. Becker
Enabling Partial Reconfiguration for Coprocessors in Mixed Criticality Multicore Systems Using PCI Express Single-Root I/O Virtualization
In 2014 International Conference on Reconfigurable Computing and FPGAs (ReConFig'14), 2014
Zusammenfassung:
Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions. In this paper, we propose a concept that leverages the advantages of FPGA's partial reconfiguration in heterogeneous mixed criticality multicore systems. We describe the basic idea how to handle the partial reconfiguration transparently for non-critical tasks, while providing full control and a predictable behavior for safety relevant tasks. Our prototype is implemented on an Intel multicore system and a Xilinx Virtex-7 FPGA connected via PCI Express (PCIe), taking advantage of the Single-Root I/O Virtualization (SR-IOV) capabilities in modern PCIe implementations. Preliminary experimental results show that our concept achieves significantly shorter reconfiguration time with lower variance compared to other solutions.
BibTeX: Anzeigen
Zusammenfassung:
Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions. In this paper, we propose a concept that leverages the advantages of FPGA's partial reconfiguration in heterogeneous mixed criticality multicore systems. We describe the basic idea how to handle the partial reconfiguration transparently for non-critical tasks, while providing full control and a predictable behavior for safety relevant tasks. Our prototype is implemented on an Intel multicore system and a Xilinx Virtex-7 FPGA connected via PCI Express (PCIe), taking advantage of the Single-Root I/O Virtualization (SR-IOV) capabilities in modern PCIe implementations. Preliminary experimental results show that our concept achieves significantly shorter reconfiguration time with lower variance compared to other solutions.
BibTeX: Anzeigen
- D. V. Vu, T. Sandmann, S. Baehr, O. Sander, J. Becker
Virtualization Support for FPGA-based Coprocessors Connected via PCI Express to an Intel Multicore Platform
In Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2014 IEEE 28th International, 2014
Zusammenfassung:
In automotive electronics, the approach to integrate several existing single-core electronics control units into a multicore computer platform is now emerging. The integration may result in mixed-criticality systems where robust segregation between software applications is crucial. Another requirement for this process is the reusability of legacy software. Virtualization is a promising technique which can help to solve these problems. In this paper, we present a hardware software co-designed virtualization support for FPGA-based coprocessors, which are connected via PCI Express to an Intel multicore platform. Experimental results show that our approach outperforms completely software-based virtualization approaches by upto 3.13 times for read and upto 26.26 times for write operations.
BibTeX: Anzeigen
Zusammenfassung:
In automotive electronics, the approach to integrate several existing single-core electronics control units into a multicore computer platform is now emerging. The integration may result in mixed-criticality systems where robust segregation between software applications is crucial. Another requirement for this process is the reusability of legacy software. Virtualization is a promising technique which can help to solve these problems. In this paper, we present a hardware software co-designed virtualization support for FPGA-based coprocessors, which are connected via PCI Express to an Intel multicore platform. Experimental results show that our approach outperforms completely software-based virtualization approaches by upto 3.13 times for read and upto 26.26 times for write operations.
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- O. Sander, T. Sandmann, D. V. Vu, S. Baehr, F. Bapp, J. Becker, H. U. Michel, D. Kaule, D. Adam, E. Lubbers, J. Hairbucher, A. Richter, C. Herber, A. Herkersdorf
Hardware virtualization support for shared resources in mixed-criticality multicore systems
In Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, S. 1-6, 2014
Zusammenfassung:
Electric/Electronic architectures in modern automobiles evolve towards an hierarchical approach where functionalities from several ECUs are consolidated into few domain computers. Performance requirements directly lead to multicore solutions but also to a combination of very different requirements on such ECUs. Using virtualization in addition is one promising way of achieving segregation in time and space of shared resources. Based on examples taken from the automotive domain several concepts for efficient hardware extensions of coprocessors and I/O devices are shown in this contribution. These provide mechanisms to ensure quality of service (QoS) levels in terms of execution time, throughput and latency. The resulting infotainment architecture is a feasibility study and is integrated into a vehicle demonstrator as centralized infotainment platform (VCT).
BibTeX: Anzeigen
Zusammenfassung:
Electric/Electronic architectures in modern automobiles evolve towards an hierarchical approach where functionalities from several ECUs are consolidated into few domain computers. Performance requirements directly lead to multicore solutions but also to a combination of very different requirements on such ECUs. Using virtualization in addition is one promising way of achieving segregation in time and space of shared resources. Based on examples taken from the automotive domain several concepts for efficient hardware extensions of coprocessors and I/O devices are shown in this contribution. These provide mechanisms to ensure quality of service (QoS) levels in terms of execution time, throughput and latency. The resulting infotainment architecture is a feasibility study and is integrated into a vehicle demonstrator as centralized infotainment platform (VCT).
BibTeX: Anzeigen
- O. Sander, F. Bapp, T. Sandmann, D. V. Vu, S. Baehr, J. Becker
Architectural Measures Against Radiation Effects in Multicore SoC for Safety Critical Applications
In IEEE 57th Midwest Symposium on Circuits and Systems (MWSCAS 14), 2014
Zusammenfassung:
It is well known that microelectronics sensitivity for radiation effects steadily increases for smaller structure sizes. Additionally lowering the supply voltage decreases safety margins even further. In conclusion modern System-on-Chip (SoC) devices, which typically come as heterogeneous multicores, can be affected by radiation effects not only in space but also in much lower altitudes or even on ground level. This is especially important for safety critical systems, such as automotive or avionics electronics. In order to cope with this issue measures during all phases of development need to be taken into account. This contribution presents and discusses techniques on architectural level, which help to detect faults on the SoC, which might be caused by (but not solely) radiation effects. Additionally these techniques have to be lightweight in terms of resources and costs as safety critical applications typically target cost sensitive markets.
BibTeX: Anzeigen
Zusammenfassung:
It is well known that microelectronics sensitivity for radiation effects steadily increases for smaller structure sizes. Additionally lowering the supply voltage decreases safety margins even further. In conclusion modern System-on-Chip (SoC) devices, which typically come as heterogeneous multicores, can be affected by radiation effects not only in space but also in much lower altitudes or even on ground level. This is especially important for safety critical systems, such as automotive or avionics electronics. In order to cope with this issue measures during all phases of development need to be taken into account. This contribution presents and discusses techniques on architectural level, which help to detect faults on the SoC, which might be caused by (but not solely) radiation effects. Additionally these techniques have to be lightweight in terms of resources and costs as safety critical applications typically target cost sensitive markets.
BibTeX: Anzeigen
Conferences and Talks
- Michael Feindt, Juergen Becker, Martin Heck, Oliver Sander und Steffen Baehr
Online-Cluster-Analyse auf FPGAs zur Separierung niederenergetischer Pionen von Untergrundteilchen
DPG Tagung 2014 Mainz
- Steffen Baehr
Recovery of slow pions
6th Belle II PXD/SVD workshop, 2014
- Steffen Baehr
Belle II PXD Hit-Recovery by Online-Cluster-Analysis on FPGAs
2nd KSETA Plenary Workshop 2015
- Steffen Bähr, Tanja Harbaum, Christian Amstutz and Uros Stevanovic
Data analysis in hardware - a tutorial on VHDL and FPGAs
KSETA Doktoranden Workshop 2013
Teaching
- Lecture Hardware Synthesis and Optimization
KSETA Reports
