Tanja Harbaum

Information Institute: ITIV Room: 226.2 (Building 30.10) Phone: +49 721 608-47169 Email: harbaum#kit.edu Website: http://www.itiv.kit.edu/english/21_3015.php

Curriculum vitae

• born July 1984
• study computer science at KIT
  
  • diversified courses:
    Robotik und Automation
    Entwurf eingebetteter Systeme und Rechnerarchitekturen
  • complementary course:
    Systems Engineering
  • Diplomarbeit „Konzeptionierung, Modellierung und anwedungs-spezifische Optimierung eines Low-Power Prozessors auf Basis der ARM Architektur“
• since March 2013 Member of Scientific Staff (ITIV)
• „Doctoral Fellow“ of Karlsruhe School of Elementary Particle and Astroparticle Physics: Science and Technology (KSETA)

Research

The CMS detector at CERN produces an extraordinary amount of data every 25ns. The Level 1 Track Trigger has to decide within a very short time to store or discard the data. Due to the latency (a couple of us) the Level 1 Track Trigger has to be implemented in a hardware system. State of the art pattern recognition approaches filter the incoming data by template matching on ASICs. We develop a new content addressable memory architecture that allows an implementation of an FPGA design.

Teaching

• excersice and assistance of lecture „Communication Systems and Protocols (CSP)“
• assistance of lecture „System-Analyse und Entwurf (SAE)”

Publications

Journals & Books

• C. Tradowsky, T. Harbaum, L. Masing, J. Becker
  A Novel ADL-based Approach to Design Adaptive Application-Specific Processors
  In Best of ISVLSI, 2015


• CMS Collaboration
  Search for supersymmetry with photons in pp collisions at s?=8??TeV
  In Physical Review Letters 92, Band 7, 2015
Zusammenfassung: Momentan nicht verfügbar
Download: Momentan nicht verfügbar
BibTeX: Anzeigen
@Incollection{Harbaum, T., title = {{A Novel ADL-based Approach to Design Adaptive Application-Specific Processors}}, author = {C. Tradowsky and T. Harbaum and L. Masing and J. Becker}, booktitle = {Best of ISVLSI}, year = {2015}, month = dec, }


• The ATLAS and CMS Collaborations
  Combined measurement of the higgs boson mass in pp collisions at s=7 and 8 TeV with the ATLAS and CMS experiments
  Physical Review Letters, Vol. 114, Nr. 19, March 2015

Conferences & Workshops

• T. Harbaum, M. Balzer, J. Becker, M. Weber
  A Content-Adapted FPGA Memory Architecture with Pattern Recognition Capability and Interval Compressing Technique
  In Proceedings of the 31th IEEE International System-on-Chip Conference (SOCC), 2018


• C Amstutz, F. Ball, M. Balzer, J. Brooke, L. Calligaris, D. Cieri, E. Clement, G. Hall, T. Harbaum, K. Harder, P. Hobson, G. Iles, T. James, K. Manolopoulos, T. Matsushita, A. Morton, D. Newbold, S. Paramesvaran, M. Pesaresi, I. Reid, A. Rose, O. Sander, T. Schuh, C. Shepherd-Themistocleous, A. Shtipliyski, S. Summers, A. Tapper, I. Tomalin, K. Uchida, P. Vichoudis, M. Weber
  Emulation of a prototype FPGA track finder for the CMS Phase-2 upgrade with the CIDAF emulation framework
  In IEEE Real Time Conference (RT), 2016


• T. Harbaum, M. Seboui, M. Balzer, J. Becker, M. Weber
  A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment
  In IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2016


• C Amstutz, F. Ball, M. Balzer, J. Brooke, L. Calligaris, D. Cieri, E. Clement, G. Hall, T. Harbaum, K. Harder, P. Hobson, G. Iles, T. James, K. Manolopoulos, T. Matsushita, A. Morton, D. Newbold, S. Paramesvaran, M. Pesaresi, I. Reid, A. Rose, O. Sander, T. Schuh, C. Shepherd-Themistocleous, A. Shtipliyski, S. Summers, A. Tapper, I. Tomalin, K. Uchida, P. Vichoudis, M. Weber
  Emulation of a prototype FPGA track finder for the CMS Phase-2 upgrade with the CIDAF emulation framework
  In IEEE Real Time Conference (RT), 2016


• C Amstutz, F. Ball, M. Balzer, J. Brooke, L. Calligaris, D. Cieri, E. Clement, G. Hall, T. Harbaum, K. Harder, P. Hobson, G. Iles, T. James, K. Manolopoulos, T. Matsushita, A. Morton, D. Newbold, S. Paramesvaran, M. Pesaresi, I. Reid, A. Rose, O. Sander, T. Schuh, C. Shepherd-Themistocleous, A. Shtipliyski, S. Summers, A. Tapper, I. Tomalin, K. Uchida, P. Vichoudis, M. Weber
  An FPGA based track finder at L1 for CMS at the High Luminosity LHC
  In IEEE Real Time Conference (RT), 2016


• C. Tradowsky, T. Harbaum, S. Deyerle, J. Becker
  LImbiC: An Adaptable Architecture Description Language Model for Developing an Application-Specific Image Processor
  In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), S. 34-39, 2013
Zusammenfassung: Due to their ease of integration and widespread adoption, General Purpose Processors (GPP) are presently used in a wide range of applications. However, the highly flexible nature of a GPP leads to overhead in terms of power, performance and area for a specific application. Another approach, proposed by this paper, is to use Application-Specific Instruction-set Processors (ASIP) that are specifically adapted to a given application. To decrease development time and effort and consequently time-to-market, a model-based development process is used. The high-level model allows for automated generation of software development tools, simulation models and RTL models from a single source. An adaptable LISA model representing a simplified ARM Cortex-M1 processor is used as a base, which is then supplemented by application-specific features requested by the software developer or system architect. This paper presents a working example of this concept, in which a state-of-the-art processor model, we call LImbiC, is extended to meet the requirements of a specific application. Specifically, custom instructions are added to the LImbiC processor to improve its performance in the particular task of image processing. In addition, during the development process infrequently used or obsoleted instructions can be removed, which allows for separate versions of LImbiC to meet varying design goals within the design space exploration.
Download: Link 
BibTeX: Anzeigen
@Inproceedings{Harbaum, T., title = {{LImbiC: An Adaptable Architecture Description Language Model for Developing an Application-Specific Image Processor}}, author = {C. Tradowsky and T. Harbaum and S. Deyerle and J. Becker}, booktitle = {IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, year = {2013}, month = aug, pages = {34-39}, doi = {10.1109/ISVLSI.2013.6654619}, }


Zusammenfassung: Due to their ease of integration and widespread adoption, General Purpose Processors (GPP) are presently used in a wide range of applications. However, the highly flexible nature of a GPP leads to overhead in terms of power, performance and area for a specific application. Another approach, proposed by this paper, is to use Application-Specific Instruction-set Processors (ASIP) that are specifically adapted to a given application. To decrease development time and effort and consequently time-to-market, a model-based development process is used. The high-level model allows for automated generation of software development tools, simulation models and RTL models from a single source. An adaptable LISA model representing a simplified ARM Cortex-M1 processor is used as a base, which is then supplemented by application-specific features requested by the software developer or system architect. This paper presents a working example of this concept, in which a state-of-the-art processor model, we call LImbiC, is extended to meet the requirements of a specific application. Specifically, custom instructions are added to the LImbiC processor to improve its performance in the particular task of image processing. In addition, during the development process infrequently used or obsoleted instructions can be removed, which allows for separate versions of LImbiC to meet varying design goals within the design space exploration.
Download: Link 
BibTeX: Anzeigen
@Inproceedings{Harbaum, T., title = {{LImbiC: An Adaptable Architecture Description Language Model for Developing an Application-Specific Image Processor}}, author = {C. Tradowsky and T. Harbaum and S. Deyerle and J. Becker}, booktitle = {IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, year = {2013}, month = aug, pages = {34-39}, doi = {10.1109/ISVLSI.2013.6654619}, }
• J. Oberlaender, T. Harbaum, G. Kurz, N. Ahmed, T. Kos-Grabar, A. Hermann, A. Roenau, R. Dillmann
  A Student-built Ball-throwing Robotic Companion for Hands-on Robotics Education
  In CLAWAR 2011, 2011
Zusammenfassung: Momentan nicht verfügbar
Download: Momentan nicht verfügbar
BibTeX: Anzeigen
@Inproceedings{Harbaum, T., title = {{A Student-built Ball-throwing Robotic Companion for Hands-on Robotics Education}}, author = {J. Oberlaender and T. Harbaum and G. Kurz and N. Ahmed and T. Kos-Grabar and A. Hermann and A. Roenau and R. Dillmann}, booktitle = {CLAWAR 2011}, year = {2011}, }


Zusammenfassung: Momentan nicht verfügbar
Download: Momentan nicht verfügbar
BibTeX: Anzeigen
@Inproceedings{Harbaum, T., title = {{A Student-built Ball-throwing Robotic Companion for Hands-on Robotics Education}}, author = {J. Oberlaender and T. Harbaum and G. Kurz and N. Ahmed and T. Kos-Grabar and A. Hermann and A. Roenau and R. Dillmann}, booktitle = {CLAWAR 2011}, year = {2011}, }

Conferences and Talks

• Tanja Harbaum
  A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment
  IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) May 2016


• Tanja Harbaum
  FPGA implementation of an Associative Memory
  CMS L1 TK meeting April 2015


• Tanja Harbaum
  CMS Level 1 Track Trigger - An FPGA Approach
  KSETA Plenary Workshop 2015


• Christian Amstutz, Tanja Harbaum and Ewa Holt
  TikZ Tutorial
  KSETA Doktoranden Workshop 2014


• Tanja Harbaum and Thomas Schuh
  FPGA-Based Architecture for Pattern Recognition
  CMS L1 TK meeting May 2014


• Steffen Bähr, Tanja Harbaum, Christian Amstutz and Uros Stevanovic
  Data analysis in hardware - a tutorial on VHDL and FPGAs
  KSETA Doktoranden Workshop 2013

KSETA Reports

• 2013
• 2014
• 2015
• 2016
• 2017
• 2018